ResearchTasksRTL SynthesisRTL SynthesisFollowBenchmarksDatasetSOTA methodSortMost resultsRecently updatedMost papersApplyDatasetSOTA methodMetricTrendResultsLast updatedVerilog-EvalSYMDIREC-GT (oracle)90.2Pass@116Mar 19, 2026VHDL-EvalSYMDIREC-GT (oracle)84.2Pass@114Mar 19, 2026VHDL-EvalStepPRM-RTL (Full)78.6Pass@18Jun 4, 2026