ResearchBenchmarksMultiplier Logic Synthesis on 16-bit multiplier (test)Multiplier Logic Synthesis on 16-bit multiplier (test)Follow1,288.5Area (µm²)Default1,265.3681,421.5091,577.651,733.791May 10, 2024Evaluation resultsMethodMethodLinksArea (µm²)Delay (ns)Default2024.051,288.52.6RL-MUL2024.051,373.62.98MCTS2024.051,734.93.19PPO+MCTS2024.051,866.81.76