Hardware Implementation on NTT
273LatencySecure NTT (baseline)
Evaluation results
| Method | Links | ||||
|---|---|---|---|---|---|
| Secure NTT (baseline)Platform=Artix-7 FPGA, # of Butterfly Unit=1, Protection=Nil, Prevent=Nil2026.01 | 273 | 1 | — | 1,028 | |
| [5]Platform=Artix-7 FPGA, # of Butterfly Unit=1, Protection=Random Memory Access, Clock Cycle Count, Prevent=SASCA, Unconventional2026.01 | 280 | 1 | — | 570 | |
| Secure NTT (protected, only detection)Platform=Artix-7 FPGA, # of Butterfly Unit=1, Protection=Back up & Independent CSR, Local Masking, Clock Cycle Counter, Prevent=CFI, Delays, SASCA2026.01 | 297 | 1 | — | 1,028 | |
| Secure NTT (protected, detection+correction)Platform=Artix-7 FPGA, # of Butterfly Unit=1, Protection=Back up & Independent CSR, Local Masking, Clock Cycle Counter, Adaptive Fault Correction, Prevent=CFI, Unconventional Delays, SASCA2026.01 | 327 | 1 | — | — | |
| [8]Platform=Artix-7 FPGA, # of Butterfly Unit=4, Protection=Partial Local Masking, Prevent=SASCA2026.01 | 1,492 | 6 | — | 237 |