CNN Inference Acceleration on Low-Bit Quantized CNNs
22.4Performance Density (GOPS/kLUT)Architecture [10]
Evaluation results
| Method | Links | |
|---|---|---|
| Architecture [10]Device=FPGA, Clock (MHz)=90, Bit Width (bits)=12021.04 | 22.4 | |
| Proposed ArchitectureDevice=ASIC, Clock (MHz)=400, Bit Width (bits)=1-22021.04 | 7.72 | |
| Architecture [21]Device=FPGA, Clock (MHz)=143, Bit Width (bits)=1-22021.04 | 4.43 |