ResearchBenchmarksArea-oriented circuit optimization on adder_architecture SSCArea-oriented circuit optimization on adder_architecture SSCFollow531.88AreaSymRTLO531.4784534.1892536.9539.6108Apr 20, 2026Evaluation resultsMethodMethodLinksAreaDelayPowerSymRTLOSynthesis Tool=Design...Synthesis Tool=Design Compiler, Optimization Objective=Area-oriented2026.04531.882.480.17OriginalSynthesis Tool=Design...Synthesis Tool=Design Compiler, Optimization Objective=Area-oriented2026.04541.922.290.17