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ASFD: Automatic and Scalable Face Detector

About

In this paper, we propose a novel Automatic and Scalable Face Detector (ASFD), which is based on a combination of neural architecture search techniques as well as a new loss design. First, we propose an automatic feature enhance module named Auto-FEM by improved differential architecture search, which allows efficient multi-scale feature fusion and context enhancement. Second, we use Distance-based Regression and Margin-based Classification (DRMC) multi-task loss to predict accurate bounding boxes and learn highly discriminative deep features. Third, we adopt compound scaling methods and uniformly scale the backbone, feature modules, and head networks to develop a family of ASFD, which are consistently more efficient than the state-of-the-art face detectors. Extensive experiments conducted on popular benchmarks, e.g. WIDER FACE and FDDB, demonstrate that our ASFD-D6 outperforms the prior strong competitors, and our lightweight ASFD-D0 runs at more than 120 FPS with Mobilenet for VGA-resolution images.

Key insights

What problem does ASFD address?

ASFD tackles accurate, efficient face detection across resource constraints using a neural architecture search feature module (Auto-FEM), a combined regression-classification loss (DRMC), and compound scaling to build a family of detectors.

How does ASFD differ from prior face detectors?

ASFD searches its feature module instead of designing it by hand. With multi-scale testing, ASFD-D6 reports 92.5% average precision on WIDER FACE's Hard validation split. Its runtime comparisons use a separate VGA-resolution setting.

What are the practical uses of ASFD?

The D0–D6 variants let developers trade detector size for accuracy. The paper reports over 100 FPS for D0/D1 on an NVIDIA P40 at VGA resolution, a hardware benchmark rather than evidence of mobile production deployment.

What limitations do the authors note?

The authors note modules with 8 intermediate nodes could only be searched with their improved method due to memory limitation. Architectural and implementation details are deferred, with a note that details will be released later.

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