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ResearchFormerly WizWand

CVDP

Benchmarks

TaskDatasetSOTA resultTrendResults

Verilog generation

CVDP cid03

44Pass@1 Rate

14

cid004: RTL – Code Modification

CVDP non-agentic 1.0

20Pass@1

13

CVDP

42.9Pass@1

12

Python reference-model generation

CVDP cid03

43.3Pass@1

10

cid016: Design Verification – Debugging / Bug Fixing

CVDP non-agentic 1.0

22.86Pass@1

10

cid007: RTL – Code Improvement (Linting / QoR)

CVDP non-agentic 1.0

51.25Pass@1

10

cid003: RTL – Natural Language Specification to Code

CVDP non-agentic 1.0

30.77Pass@1

10

cid002: RTL – Code Completion

CVDP non-agentic 1.0

24.47Pass@1

10

RTL Design Code Generation

CVDP cid03

39Function Accuracy

8

RTL Design Code Generation

CVDP cid02

22.4Function Accuracy

8

Code comprehension

CVDP (Code Verilog Design Problems) (test)

106Total Passes

8