Interrupt Handling Characterization on RV32IM core Xilinx XC7K410T FPGA platform
5Interrupt LatencyBase
Evaluation Results
| Method | Links | ||||
|---|---|---|---|---|---|
| BaseDescription=RV32IM core baseline2026.04 | 5 | 0.0931 | 2.07 | 30.48 | |
| Base+V5Extension=V5, IID=CAM, Register context=banked, TCM ports=dedicated for protection tables and register spills2026.04 | 11 | 0.1372 | 2.89 | 33.75 | |
| Base+V4Extension=V42026.04 | 14 | 0.1269 | 2.74 | 35.1 | |
| Base+V3Extension=V32026.04 | 17 | 0.1257 | 2.73 | 33.85 | |
| Base+V2Extension=V2, IID=table, Register context=stack, TCM ports=dedicated for stack2026.04 | 29 | 0.1058 | 2.3 | 32.6 | |
| Base+V1Extension=V1, IID=table, Register context=stack, TCM ports=none2026.04 | 38 | 0.1105 | 2.44 | 31.75 | |
| KernelDescription=Microkernel software path2026.04 | 634 | — | — | — |