# AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning Source: [AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning]() Collection index: [llms.txt]() Data updated: 2026-04-30T05:00:04.703Z Authors: Chongxiao Li, Pengwei Jin, Di Huang, Guangrun Sun, Husheng Han, Jianan Mu, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Hanjun Wei, Tianyun Ma, Shuyao Cheng, Rui Zhang, Ying Wang, Zidong Du, Qi Guo, Xing Hu Published: 2026-04-20T16:02:04.000Z ## Abstract Performance, power, and area (PPA) optimization is a fundamental task in RTL design, requiring a precise understanding of circuit functionality and the relationship between circuit structures and PPA metrics. Recent studies attempt to automate this process using LLMs, but neither feedback-based nor knowledge-based methods are efficient enough, as they either design without any prior knowledge or rely heavily on human-summarized optimization rules. In this paper, we propose AutoPPA, a fully automated PPA optimization framework. The key idea is to automatically generate optimization rules that enhance the search for optimal solutions. To do this, AutoPPA employs an Explore-Evaluate-Induce ($E^2I$) workflow that contrasts and abstracts rules from diverse generated code pairs rather than manually defined prior knowledge, yielding better optimization patterns. To make the abstracted rules more generalizable, AutoPPA employs an adaptive multi-step search framework that adopts the most effective rules for a given circuit. Experiments show that AutoPPA outperforms both the manual optimization and the state-of-the-art methods SymRTLO and RTLRewriter. ## Recorded benchmark results A research result applies to its stated dataset, split, metric and evaluation configuration. Compare like-for-like settings, preserve the metric's unit and direction, and distinguish paper-reported results from independent reproduction. The best result recorded here is not a claim of exhaustive, current global coverage. - [RTL Design Optimization on 60 circuits](): RTL Design Optimization; 60 circuits; Improvement @15 (Area): 9.56. - [Area-oriented circuit optimization on subexp\_elim SMIC 12nm](): Area-oriented circuit optimization; subexp\_elim SMIC 12nm; Area: 116.81. - [Area-oriented circuit optimization on subexp\_elim TSMC 65nm](): Area-oriented circuit optimization; subexp\_elim TSMC 65nm; Area: 1130.04. - [Area-oriented circuit optimization on adder\_architecture TSMC 65nm](): Area-oriented circuit optimization; adder\_architecture TSMC 65nm; Area: 79.92. - [Area-oriented circuit optimization on vending\_machine SMIC 12nm](): Area-oriented circuit optimization; vending\_machine SMIC 12nm; Area: 2966.91. - [Area-oriented circuit optimization on fft SMIC 12nm](): Area-oriented circuit optimization; fft SMIC 12nm; Area: 27769.19. - [Area-oriented circuit optimization on vending\_machine TSMC 65nm](): Area-oriented circuit optimization; vending\_machine TSMC 65nm; Area: 29798.64. - [Area-oriented circuit optimization on fft TSMC 65nm](): Area-oriented circuit optimization; fft TSMC 65nm; Area: 262633.7. - [RTL Optimization on RTLRewriter circuit designs (example1)](): RTL Optimization; RTLRewriter circuit designs (example1); Area: 29.26. - [RTL Optimization on RTLRewriter circuit designs (com\_subexp)](): RTL Optimization; RTLRewriter circuit designs (com\_subexp); Area: 11310.85. - [RTL Optimization on RTLRewriter circuit designs m\_con\_mul](): RTL Optimization; RTLRewriter circuit designs m\_con\_mul; Area: 876.47. - [Area-oriented circuit optimization on Average Improvement TSMC 65nm](): Area-oriented circuit optimization; Average Improvement TSMC 65nm; Area Improvement (%): 18.93. - [RTL Optimization on RTLRewriter circuit designs](): RTL Optimization; RTLRewriter circuit designs; Area Change: 20.45. - [Area-oriented circuit optimization on spmv SMIC 12nm](): Area-oriented circuit optimization; spmv SMIC 12nm; Area: 295.28. - [Area-oriented circuit optimization on spmv TSMC 65nm](): Area-oriented circuit optimization; spmv TSMC 65nm; Area: 2904.12. - [RTL Optimization on RTLRewriter circuit designs mux\_type1](): RTL Optimization; RTLRewriter circuit designs mux\_type1; Area: 2.13. - [Area-oriented circuit optimization on Average Improvement SMIC 12nm](): Area-oriented circuit optimization; Average Improvement SMIC 12nm; Area Improvement (%): 18.12. - [Area-oriented circuit optimization on adder\_architecture SMIC 12nm](): Area-oriented circuit optimization; adder\_architecture SMIC 12nm; Area: 8.48. - [RTL Optimization on RTLRewriter circuit designs add3](): RTL Optimization; RTLRewriter circuit designs add3; Area: 65.17. - [Area-oriented circuit optimization on spmv SSC](): Area-oriented circuit optimization; spmv SSC; Area: not recorded. - [Area-oriented circuit optimization on subexp\_elim SSC](): Area-oriented circuit optimization; subexp\_elim SSC; Area: not recorded. - [Area-oriented circuit optimization on adder\_architecture SSC](): Area-oriented circuit optimization; adder\_architecture SSC; Area: not recorded. - [Area-oriented circuit optimization on vending\_machine SSC](): Area-oriented circuit optimization; vending\_machine SSC; Area: not recorded. - [Area-oriented circuit optimization on fft SSC](): Area-oriented circuit optimization; fft SSC; Area: not recorded. - [Area-oriented circuit optimization on SSC](): Area-oriented circuit optimization; SSC; Area: not recorded. ## Original sources and implementation [Original paper]() [PDF]()