# Implementation of high-efficiency, lightweight residual spiking neural network processor based on field-programmable gate arrays

Source: [Implementation of high-efficiency, lightweight residual spiking neural network processor based on field-programmable gate arrays](<https://www.sota2.com/research/paper/695c96d653fdd5c36174331c>)

Collection index: [llms.txt](<https://www.sota2.com/research/llms.txt>)

Data updated: 2026-01-07T05:00:04.580Z

Authors: Hou Yue, Xiang Shuiying, Zou Tao, Huang Zhiquan, Shi Shangxuan, Guo Xingxing, Zhang Yahui, Zheng Ling, Hao Yue

Published: 2025-12-09T02:08:46.000Z

## Abstract

With the development of hardware-optimized deployment of spiking neural networks (SNNs), SNN processors based on field-programmable gate arrays (FPGAs) have become a research hotspot due to their efficiency and flexibility. However, existing methods rely on multi-timestep training and reconfigurable computing architectures, which increases computational and memory overhead, thus reducing deployment efficiency. This work presents an efficient and lightweight residual SNN accelerator that combines algorithm and hardware co-design to optimize inference energy efficiency. In terms of the algorithm, we employ single-timesteps training, integrate grouped convolutions, and fuse batch normalization (BN) layers, thus compressing the network to only 0.69M parameters. Quantization-aware training (QAT) further constrains all parameters to 8-bit precision. In terms of hardware, the reuse of intra-layer resources maximizes FPGA utilization, a full pipeline cross-layer architecture improves throughput, and on-chip block RAM (BRAM) stores network parameters and intermediate results to improve memory efficiency. The experimental results show that the proposed processor achieves a classification accuracy of 87.11% on the CIFAR-10 dataset, with an inference time of 3.98 ms per image and an energy efficiency of 183.5 FPS/W. Compared with mainstream graphics processing unit (GPU) platforms, it achieves more than double the energy efficiency. Furthermore, compared with other SNN processors, it achieves at least a 4x faster inference speed and a 5x higher energy efficiency.

## Recorded benchmark results

A research result applies to its stated dataset, split, metric and evaluation configuration. Compare like-for-like settings, preserve the metric's unit and direction, and distinguish paper-reported results from independent reproduction. The best result recorded here is not a claim of exhaustive, current global coverage.

- [Image Classification on CIFAR-10 (Accuracy, Power, Delay)](<https://www.sota2.com/research/sota/image-classification-on-cifar-10-accuracy-power-delay.md>): Image Recognition; CIFAR-10; Accuracy: 87.11.

## Original sources and implementation

[Original paper](<https://arxiv.org/abs/2601.00802>)

[PDF](<https://arxiv.org/pdf/2601.00802.pdf>)