# HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design Source: [HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design]() Collection index: [llms.txt]() Data updated: 2025-10-26T05:54:15.806Z Authors: Jinwei Tang, Jiayin Qin, Kiran Thorat, Chen Zhu-Tian, Yu Cao, Yang (Katie) Zhao, Caiwen Ding Published: 2024-12-06T19:37:53.000Z ## Abstract With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs. ## Recorded benchmark results A research result applies to its stated dataset, split, metric and evaluation configuration. Compare like-for-like settings, preserve the metric's unit and direction, and distinguish paper-reported results from independent reproduction. The best result recorded here is not a claim of exhaustive, current global coverage. - [Verilog Generation on VerilogEval v2 (41 filtered problems)](): Verilog Generation; VerilogEval v2 (41 filtered problems); Solved Rate: 0.6585365853658537. ## Original sources and implementation [Original paper]() [PDF]()