# VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Source: [VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool](<https://www.sota2.com/research/paper/68fa77481e209131cea72380>)

Collection index: [llms.txt](<https://www.sota2.com/research/llms.txt>)

Data updated: 2025-10-26T04:14:52.638Z

Authors: Chia-Tung Ho, Haoxing Ren, Brucek Khailany

Published: 2024-08-15T20:06:06.000Z

## Abstract

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

## Recorded benchmark results

A research result applies to its stated dataset, split, metric and evaluation configuration. Compare like-for-like settings, preserve the metric's unit and direction, and distinguish paper-reported results from independent reproduction. The best result recorded here is not a claim of exhaustive, current global coverage.

- [Verilog Generation on VerilogEval v2 (41 filtered problems)](<https://www.sota2.com/research/sota/verilog-generation-on-verilogeval-v2-41-filtered-problems.md>): Verilog Generation; VerilogEval v2 (41 filtered problems); Solved Rate: 0.7804878048780488.

- [Verilog Generation on VerilogEval v2](<https://www.sota2.com/research/sota/verilog-generation-on-verilogeval-v2.md>): Verilog Generation; VerilogEval v2; Pass@1: not recorded.

## Original sources and implementation

[Original paper](<https://arxiv.org/abs/2408.08927>)

[PDF](<https://arxiv.org/pdf/2408.08927.pdf>)