# Exploring the Vision Processing Unit as Co-processor for Inference

Source: [Exploring the Vision Processing Unit as Co-processor for Inference](<https://www.sota2.com/research/paper/68fa64e21e209131cea07114>)

Collection index: [llms.txt](<https://www.sota2.com/research/llms.txt>)

Data updated: 2025-10-28T13:56:37.009Z

Authors: Sergio Rivas-Gomez, Antonio J. Pe\\~na, David Moloney, Erwin Laure, Stefano Markidis

Published: 2018-10-09T17:37:14.000Z

## Abstract

The success of the exascale supercomputer is largely debated to remain dependent on novel breakthroughs in technology that effectively reduce the power consumption and thermal dissipation requirements. In this work, we consider the integration of co-processors in high-performance computing (HPC) to enable low-power, seamless computation offloading of certain operations. In particular, we explore the so-called Vision Processing Unit (VPU), a highly-parallel vector processor with a power envelope of less than 1W. We evaluate this chip during inference using a pre-trained GoogLeNet convolutional network model and a large image dataset from the ImageNet ILSVRC challenge. Preliminary results indicate that a multi-VPU configuration provides similar performance compared to reference CPU and GPU implementations, while reducing the thermal-design power (TDP) up to 8x in comparison.

## Recorded benchmark results

A research result applies to its stated dataset, split, metric and evaluation configuration. Compare like-for-like settings, preserve the metric's unit and direction, and distinguish paper-reported results from independent reproduction. The best result recorded here is not a claim of exhaustive, current global coverage.

## Original sources and implementation

[Original paper](<https://arxiv.org/abs/1810.04150>)

[PDF](<https://arxiv.org/pdf/1810.04150.pdf>)