# Reversible and irreversible trapping at room temperature in poly(thiophene) thin-film transistors

Source: [Reversible and irreversible trapping at room temperature in poly(thiophene) thin-film transistors](<https://www.sota2.com/research/paper/68fa26df2c2a3760193be23f>)

Collection index: [llms.txt](<https://www.sota2.com/research/llms.txt>)

Data updated: 2025-10-24T11:40:29.716Z

Authors: A. Salleo, F. Endicott, R. A. Street

Published: 2005-02-28T20:10:49.000Z

## Abstract

We measured the bias stress characteristics of poly(thiophene) semi-crystalline thin-film transistors (TFTs) as a function stress times, gate voltages and duty-cycles. At room temperature, the bias stress has two components: a fast reversible component and a slow irreversible component. We hypothesize that the irreversible component is due to charge trapping in the disordered areas of the semiconductor film. At low duty-cycle (\<2%), the fast bias stress component is reversed during the off-part of the cycle therefore the observed VT shift in only caused by irreversible trapping. Irreversible trapping follows power-law kinetics with a time exponent approximately equal to 0.37. We use these findings to estimate the lifetime of TFTs used as switches in display backplanes.

## Recorded benchmark results

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## Original sources and implementation

[Original paper](<https://arxiv.org/abs/cond-mat/0502642>)

[PDF](<https://arxiv.org/pdf/cond-mat/0502642.pdf>)